1. Field of the Invention
The present invention relates generally to field effect transistors (FET's) formed as complimentary metal oxide semiconductor (CMOS) structures and, more particularly, to new and improved MOSFET devices having vertically oriented channel structures capable of fully depleted operation. Specifically, the present invention relates to an improved vertically oriented MOSFET device and method of fabrication thereof which incorporates a tetrode gate structure, thereby providing an integrated cascode for high performance analog and mixed-signal applications.
2. Description of the Prior Art
The progression of CMOS device scaling, that is planer MOSFET, has seen a continuous shrinking of transistor dimensions in both the vertical and the horizontal dimensions resulting in an approximate doubling of the number of transistors per unit area every 18 months or so. From the economics perspective, this scaling progression has resulted in CMOS becoming the preeminent technology for packing system functions on a transistor chip. The desire to shrink gate channel lengths and hence area, as width-to-length ratios remain roughly constant, requires the simultaneous vertical scaling of both the gate oxide and the source/drain junctions. This creates the requirement that the power supply (Vdd) also scale, as indicated above. The power supply voltage must scale so as to maintain gate oxide integrity (breakdown/wear-out due to voltage stress), to provide adequate junction breakdown margin, and to minimize device lifetime reduction due to hot carrier injection.
While CMOS scaling has enabled the circuit and system designer to pack a tremendous amount of functionality onto a silicon die, it has simultaneously created a number of significant problems as far as the chip's ability to interface with the outside world. This is particularly true in the area of analog/digital mixed-signal chips, and in particular for communication and power management applications which may be used or exist in a less-controlled signaling environment than found in all-digital systems. Some examples of the efforts to overcome this are illustrated in U.S. Pat. Nos. 4,393,391, 4,583,107, 5,675,164, 5,801,417, 5,932,911, 6,111,296, 6,118,161, 6,207,511, 6,396,108, and 6,413,802.
The continuing drive to utilize semiconductor chip area while maintaining I/O compatibility has resulted in the evolution of baseline CMOS ASIC/SOC process technologies that now have two gate oxides to account for the need to operate efficiently at two, and sometimes three, power supply levels. Having begun at roughly the 0.25 um node, this is currently the approach taken by certain mainstream ASIC/ASSP semiconductor producers or foundries. These technology offerings generally consist of a baseline process flow that has a fully scaled and optimized thin oxide core device to the extent that the current process manufacturing technology allows, and a thick oxide device which is essentially the core device from the previous technology generation. Unfortunately, in such technology evolution, the thick oxide I/O device has become somewhat of a “forgotten stepchild”, as only the thin-oxide core devices can truly take advantage of the shrinking feature sizes that are enabled by state-of-the-art photolithography. More importantly, as the thick oxide device is a “leftover” from the previous technology node, it typically under-performs the thin-oxide core device in terms of speed/bandwidth (ft).
The impact of this trend is particularly acute in the area of all-CMOS analog and mixed analog/digital signal chips. These chips derive their advantage from the ability to integrate complex digital core functions, such as DSP, with analog signal processing functions, such as analog-to-digital or digital-to-analog converters. While this reliability-driven voltage trend results in lower power consumption for digital functions, the effect is not necessarily the same in the analog case. In fact, it has been shown that in an analog-to-digital converter application with a fixed dynamic range requirement, power consumption can actually increase with decreasing power supply.
At present, BiCMOS (bipolar-CMOS combination) technologies, and particularly SiGe bipolar, offer a solution to some of the problems discussed above. However, a number of difficulties persist including, in particular, power consumption, cost and scalability. Bipolar devices consume significantly more power than CMOS devices, which increases package cost and at some point renders them unsuitable as a system solution, in particular for portable devices. From the standpoint of scaling, bipolar technologies have hit an apparent limit in terms of increasing performance for a given density and power consumption. The integration of CMOS and bipolar devices (BiCMOS) reduces the power consumption problem but leads to a second difficulty, i.e. cost. High performance technologies, such as SiGe BiCMOS cost upwards of 25% or more than CMOS devices at the same feature sizes. Finally, bipolar devices by nature, like the thick oxide CMOS I/O devices discussed earlier, cannot take full advantage of decreasing feature sizes which result from advances in wafer patterning technology (photolithography).
Clearly, the trends and problems discussed above may soon create a situation where it is no longer desirable to integrate a significant amount of analog functionality into a single-chip mixed-signal system solution, thus eliminating one of the traditional paths to reduce cost and power consumption in electronic systems. Recently new device structures have been proposed to provide solutions which overcome the aforementioned problems, as is detailed in U.S. Pat. No. 7,212,864, mentioned in the cross-reference subsection of this application. As shown in FIG. 1, the prior art castellated gate MOSFET triode device 3 (or alternately, FDCG MOSFET) is a non-planar structure having lateral current flow through a plurality of semiconductor channels. While the prior art device of U.S. Pat. No. 7,212,864 provides a number of solutions to the analog and mixed-signal problem in all-CMOS technologies, some problems still exist in the quest to provide still higher performance and robustness.
One of the more persistent problems in the area of three terminal electron devices, and field effect transistors in particular, is the well known trade-off between device series resistance (Rdsw) and parasitic gate-to-drain, or source capacitance. Elements of this problem were encountered early on during the era of the vacuum tube triode, leading to the development of the vacuum tube tetrode (British Patent No. 145,421, 1921), wherein an auxiliary screen grid was added which substantially reduced the miller capacitance between the primary control grid and the anode. In summary, the addition of an additional control electrode resulted in the creation of a compound device that had the functional features of a cascode circuit arrangement of two triode devices.
Moving forward to the semiconductor era, multiple gate arrangements 5 were proposed for Field Effect devices, as shown in FIG. 2, to solve a similar set of problems (U.S. Pat. No. 3,803,461). These prior art FET devices were later utilized in a number of novel RF circuit topologies 7, as shown in FIG. 3 (U.S. Pat. No. 4,167,681). Recently, as shown in FIG. 4, a novel discrete power HEMT FET device 9, utilizing an integrated cascode structure 10, has been disclosed to improve the performance of solid-state RF power amplifiers (U.S. Pat. No. 7,126,426).
More specifically, in the case of vertically oriented field effect devices, the utilization of multiple gate electrodes have been proposed for a large number of purposes. For example, FIG. 5 illustrates a prior art vertical fin device 15 which utilizes multiple gates to control a common primary channel structure (U.S. Pat. No. 7,126,426). One application of such a gate arrangement is to facilitate the implementation of multiple-threshold logic circuits for digital computing applications. This is a substantially different application of multiple gate electrode structures than the device of the present invention.
A more pertinent example of a vertical prior art device is shown in FIG. 6 (U.S. Pat. No. 7,105,934). Prior art FinFET device 16, preferably fabricated on a Silicon-On-Insulator (SOI) starting substrate, utilizes multiple gates connected as a common node to control primary and secondary channel structures, and thereby has reduced extrinsic device series resistance. In the case of the device of FIG. 6, the utilization of a single gate node is advantageous for realizing digital circuit functions, the efficiency of which can be substantially limited by interconnect density considerations. In the case of analog and mixed-signal functions however, where interconnect density considerations are typically more relaxed, the co-modulation of differing adjoined channel structures may introduce non-linearity, thereby reducing the effectiveness of the device.
In spite of the improvements that have been discussed in the area of multiple-gate MOS Field Effect devices, a number of problems remain to be solved, particularly in the domain of CMOS analog and mixed-signal circuit applications. The device of the present invention addresses and solves a number of additional problems in the art.